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# 1   2010-06-24 10:48:51 Two timers counting on opposite levels of external signal

alpha
New member
Registered: 2010-06-24
Posts: 5

Two timers counting on opposite levels of external signal

Hello

I am a bit stuck at the moment, and would appreciate some input:

I am trying to setup TIM1 and TIM2 so that they will count on opposite levels of an external signal. It is a bit like the PWM-input mode, but it must be able to get a count for several periods of the signal.

Any ideas ?

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# 2   2010-06-24 18:51:35 Two timers counting on opposite levels of external signal

brothe_r
Member
Registered: 2010-04-08
Posts: 10

Re: Two timers counting on opposite levels of external signal

Hi alpha,

When you use the input PWM mode you have 2 registers: the period and the cycle counter. The cycle counter is the counter from rise edge to fall edge of the input signal, and the period counter from rise edge to rise edge of the input signal. If you divide cycle counter by period counter * 100, you can know the cycle % of the input signal, regardless if you have a variable period time.

Is that what are you asking for?

Hope to help

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# 3   2010-06-28 07:58:50 Two timers counting on opposite levels of external signal

alpha
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Registered: 2010-06-24
Posts: 5

Re: Two timers counting on opposite levels of external signal

thanks for the input, but it's not quite what I was thinking. I need to get the time the signal is low and high for several periods, since the signal is to fast for the interrupts of the CC. What I'm trying to do is to detect a 180degree phase shift. When the signal shifts phase the period will be longer than normal. Since the signal is at 1.5MHz, I lose a lot of the periods while being in the interrupt routine if i use the PWM input mode.

I'm simply trying to get one counter to only count while the signal is low, and another to count while the signal is high. This should give me a bit more time to handle the data, since I don't need to do something every cycle of the input signal, but can handle more cycles at a time.

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# 4   2010-06-28 09:23:27 Two timers counting on opposite levels of external signal

diabolo38
Member
Registered: 2010-03-12
Posts: 50

Re: Two timers counting on opposite levels of external signal

brothe_r :

Hi alpha,

When you use the input PWM mode you have 2 registers: the period and the cycle counter. The cycle counter is the counter from rise edge to fall edge of the input signal, and the period counter from rise edge to rise edge of the input signal. If you divide cycle counter by period counter * 100, you can know the cycle % of the input signal, regardless if you have a variable period time.

Is that what are you asking for?

Hope to help

I guess it should be ok...
rise edge to fall edge  ->signal high time
"edge to edge "  -> full period time

Full period time - "signal high time" = "signal low time"
So don't you have in this mode all the information you are looking for  ?

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# 5   2010-06-28 09:29:34 Two timers counting on opposite levels of external signal

alpha
New member
Registered: 2010-06-24
Posts: 5

Re: Two timers counting on opposite levels of external signal

Yes, I have all the information, but because the signal is so fast, it's no time to run an interrupt routine at every period of the signal, and so some periods are lost. Since I'm looking for a spesific period where the phase shift appears, it won't get detected. What I need is to get high and low time, but for more than one single period as it is with the pwm input mode. If I can count the high/low time for 5-6 periods it's enough time to run an interrupt routine, and check if a phase shift occured.

to illustrate what the signal looks like:


HLHLHLHLLHLHLHLHLHHLHL

where H is high and L is low, and the phase shifts occur where there is a double H or double L.

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# 6   2010-06-28 19:37:07 Two timers counting on opposite levels of external signal

ntrf.zns
Member
From: Belgorod, Russia
Registered: 2009-11-01
Posts: 134

Re: Two timers counting on opposite levels of external signal

Sounds to me it would be easier to capture values in exact time periods. You can configure DMA to capture a cyclic buffer of ANY data when triggered by timer. This is much better solution if you do know the exact data rate. If you do know the maximum data packet length you can use non-cyclic buffer. When you get full buffer (or half for cyclic mode) - analyse it in software.

If you don't know exact data rate but you do have some kind of preamble you can configure timers while watching the pin state in cicle. It won't take too long to impact overal performance or battery usage.

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# 7   2010-06-29 23:21:11 Two timers counting on opposite levels of external signal

brothe_r
Member
Registered: 2010-04-08
Posts: 10

Re: Two timers counting on opposite levels of external signal

OK, I understand... Well, some STM32 may reach up to 72MHz (the worst case of 36MHz), it seems like it can handle a signal of 1.5MHz...

Anyway, you could also use the input capture mode, that is, you have a register which only increments when an input pin is at a desired state. So, when the signal is high, one register would increment (at the rate of the timer clock), while when low, another register would increment (you should use 2 intput pins of the STM32). This would solve the problem in the way you thought. But the problem of doing it in this way, is you may have problems like this:

HLHLHLHLLHLHLHHLHL

In the previous case, there are 2 low states, and 2 high states in the chain. So, you will finally have the same value in both registers, and you couldn't identify the change in phase case... Well, if you just have high states like in your previous example instead of several high and several low it could be useful.

Another possible solution: Do you have one single signal or two? If you have two, maybe you could use a quadrature decoder... Or if you just have one, you could generate another signal with 50% of duty cycle at the same frequency (1.5MHz) with a PWM peripheral, to add the second signal and to be able to use the quadrature decoder.

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# 8   2010-06-30 05:52:09 Two timers counting on opposite levels of external signal

alpha
New member
Registered: 2010-06-24
Posts: 5

Re: Two timers counting on opposite levels of external signal

I am currently testing with the pwm input mode and cyclic DMA. This seems to be working, and it's enough time to do the decoding in the interrupt routine.
Thanks for all the help.

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