STM CircleOS forum / Is bit banding not really possible on GPIO data registers?

sentinel · 2010-04-28 21:29:44

The insiders guide to STM32 gives an example in which the data port is controlled by aliasing it to bit banding region. The data sheet allows only word access to those registers. In practice bit banding seem to be working fine. What is the real situation with it?
thanks.

yrt · 2010-04-29 08:30:37

I found only a SRAM access by bit banding in the ST library examples. Where did you find your example ?
But effectively, the reference manual indicates two bit banding areas (peripheral and SRAM).

sentinel · 2010-04-29 14:21:05

Page 17 of the "insider's guide to STM32" says:

Quote
This is much easier than it may look at first glance. For a practical example, the GPIO output data register is
written to in order to set and clear individual IO lines. The physical address of the Port B output register is
0x40010C0C. In this example we want to be able to set and clear bit eight of this word using the above formula.
Word address = 0x40010C0C
Peripheral bit band base = 0x40000000
Peripheral bit band Alias base = 0x42000000
Byte offset from bit band base = 0x40010c0c – 0x40000000 = 10c0c
Bit word offset = (0x10c0c x 0x20) +(8x4) = 0x2181A0
Bit Alias address = 0x42000000 + 0x2181A0 = 0x422181A0
We can now create a pointer to this address using the following line of C:
#define PortBbit8 (*((volatile unsigned long *) 0x422181A0 ))
This pointer can then be used to set and clear the IO port bit:
PB8 = 1; //led on
Which generates the following assembly instructions:...
Unquote

Btw, it does work - setting individual bits in a port ODR by aliasing it to the bit band area. The question - why does it work? Is it legitimate? Can we use it contrary to the data sheet? Reading port bits seem to work fine too. But will it work always?

As for the peripheral area for bit banding - yes, we can use it because most of peripheral registers don't have that access condition - word access only, as GPIO data registers have.

Matthias · 2010-04-29 20:47:40

with GPIO, it is possible
Here is an example of 8 bits to port e (PE 7.PE14)

GPIOE-> BSRR = ((u32) 0x7F800000) | ((a) <<7)

sentinel · 2010-04-29 21:42:17

Matthias, of course what you suggest is totally fine. It is a normal word access. I was talking about bit banding, so that you can create a single define that would map a port pin to an alias of ODR register in the alias memory. Then you can define and use something like
LED_1 = 1;
or LED_1 = 0,
and it will be an atomic set OR clear of a port pin by a simple write of "1" or "0" to a memory address, the SAME memory address.
The alternative would be to have two different defines to control the LED_1: one to set it (by writing to BSRR), the other - to clear it (by writing to BRR or another location in BSRR). The code would look like
SET_LED_1;
or CLR_LED_1;

Note that in the first case we would use the ODR register. In the second - BSRR and/or BRR.
Reading of a bit would also be more complicated because you can't get status of a bit from the IDR without masking the needed bit and shifts if you want to get either "0x1" or "0x0". Aliasing it to bit banding would compile as one read from a memory location that would yield either "0" or "1" in the LSB of the result. It is more compact, cleaner and faster. But the question remains " Is it legitimate? Does a port register see the access via bit alias as a normal word access? " I am afraid that only people from ST can confirm it.

justinx · 2012-06-07 20:35:39

Related to this post. Can someone confirm two points for me:

1) For atomic write to GPIO pins use the BSSR register.

2) For atomic read of a GPIO pin you must use a bitband.

yrt · 2012-06-08 06:41:11

$1 : In the Reference Manual it is indicated that "In the STM32F10xxx both peripheral registers and SRAM are mapped in a bit-band region".

$1 : the reference manual says "Each I/O port bit is freely programmable, however the I/O port registers have to be accessed
as 32-bit words (half-word or byte accesses are not allowed). The purpose of the
GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of
the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the
modify access."

# 1 2010-04-28 21:29:44 Is bit banding not really possible on GPIO data registers?

Is bit banding not really possible on GPIO data registers?

# 2 2010-04-29 08:30:37 Is bit banding not really possible on GPIO data registers?

Re: Is bit banding not really possible on GPIO data registers?

# 3 2010-04-29 14:21:05 Is bit banding not really possible on GPIO data registers?

Re: Is bit banding not really possible on GPIO data registers?

# 4 2010-04-29 20:47:40 Is bit banding not really possible on GPIO data registers?

Re: Is bit banding not really possible on GPIO data registers?

# 5 2010-04-29 21:42:17 Is bit banding not really possible on GPIO data registers?

Re: Is bit banding not really possible on GPIO data registers?

# 6 2012-06-07 20:35:39 Is bit banding not really possible on GPIO data registers?

Re: Is bit banding not really possible on GPIO data registers?

# 7 2012-06-08 06:41:11 Is bit banding not really possible on GPIO data registers?

Re: Is bit banding not really possible on GPIO data registers?

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