A bit of research on this CPU (tricky, ST doesn't document the CPU, that's ARM's job) indicates there are "Sleep on Exit" modes that might be set wrong. Refer to Section 5.9.2 in the Cortex M3 Technical Reference Manual at or about <http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/ch05s09s02.html>. The CPU initialisation might have "Sleep on Exit" enabled which would explain these problems. Section 7,2 says "Sleep-on-exit might return to base under various situations such as debug. Therefore, you must provide base code such as an idle loop or idle thread."
It might also be due to if/how the SLEEPING and SLEEPDEEP hardware signals are handled in hardware. Details on this in section 7.2 as well.