Thanks for looking into it Francis. But I cannot relate what you are explaining to the datahseet,
and other projects (examples) provided by ST.
When the STM32 boots, SYSCLOCK is derived from HSI (chapter 4.2.6 of datasheet). There should be no need
to specify in the code to use it as a SYSCLOCK, as it is the only clock enabled at bootup anyway.
Also, in scheduler.c,
We are starting the HSE clock with:
RCC_HSEConfig( RCC_HSE_ON );
Then we are waiting (blocking) for the HSE clock to be ready
while( RCC_GetFlagStatus( RCC_FLAG_HSERDY ) == RESET )
{;}
This means that the whole application is blocked up to the moment the HSE is ready.
A few lines below, we find the jump to UTIL_SetPll() which sets only at that time in the code the SYSCLOCK
as being HSI. But why then, as by then HSE is ready to go anyway. You suggested we are starting from HSI while
waiting the PLL to stabilize. But that does not match what the code does, as we enable the HSE (while
HSI is the only clock running), we wait for HSE to stabilize and then we switch to HSI to finally switch back
to HSE clock a few line below in UTIL_SetPll().
If you look at example5 provided in the I2C example set from STLib, you will see that they set SYSCLOCK to HSE in main.c, and that is it. They do not seem to switch from HSI to HSE in their example. I check also other projects (non OS Circle related), and no one is really switching back and forth for standard application (no power down, etc.).
The following way of proceeding makes more sense to me, if you don't mind:
void RCC_Configuration(void)
{
/* RCC system reset(for debug purpose) */
RCC_DeInit();
/* Enable HSE */
RCC_HSEConfig(RCC_HSE_ON);
/* Wait till HSE is ready */
HSEStartUpStatus = RCC_WaitForHSEStartUp();
if(HSEStartUpStatus == SUCCESS)
{
/* Enable Prefetch Buffer */
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
/* Flash 2 wait state */
FLASH_SetLatency(FLASH_Latency_2);
/* HCLK = SYSCLK */
RCC_HCLKConfig(RCC_SYSCLK_Div1);
/* PCLK2 = HCLK */
RCC_PCLK2Config(RCC_HCLK_Div1);
/* PCLK1 = HCLK/2 */
RCC_PCLK1Config(RCC_HCLK_Div2);
/* PLLCLK = 12MHz * 6 = 72 MHz */
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_6);
/* Enable PLL */
RCC_PLLCmd(ENABLE);
/* Wait till PLL is ready */
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
{
}
/* Select PLL as system clock source */
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
/* Wait till PLL is used as system clock source */
while(RCC_GetSYSCLKSource() != 0x08)
{
}
}
A final thought for UTIL_SetPll().
The first two lines have wrong comments. That puzzels me. Does this say something? Are those lines old lines,
not being removed when the code was finalized?
/* Select PLL as system clock source */
RCC_SYSCLKConfig( RCC_SYSCLKSource_HSI );
/* Enable PLL */
RCC_PLLCmd( DISABLE );
Thanks for your continued and very good support Francis,
