CircleOS  1
Util_spe2.c
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1 /****************** COPYRIGHT (C) 2007-2013 KEOLABS S.A.S. ********************/
11 /******************************************************************************/
12 
13 /* Includes ------------------------------------------------------------------*/
14 #include "circle.h"
15 
17 
18 /* Private defines -----------------------------------------------------------*/
19 #define VDD_VOLTAGE_MV 3150 /* Voltage (mV) of the STM32*/
20 
21 /* Private typedef -----------------------------------------------------------*/
22 
23 /* Private variables ---------------------------------------------------------*/
24 RCC_ClocksTypeDef RCC_ClockFreq;
25 s16 VBat = -1;
26 
27 /* Private function prototypes -----------------------------------------------*/
28 
29 /* Private functions ---------------------------------------------------------*/
30 
31 /* External variables ---------------------------------------------------------*/
32 
33 /* Public functions ----------------------------------------------------------*/
34 
35 /*******************************************************************************
36 *
37 * UTIL_isBackupRegisterConfigured
38 *
39 *******************************************************************************/
47 /******************************************************************************/
48 bool UTIL_isBackupRegisterConfigured( void )
49 {
50  int i;
51 
52  for ( i = 1 ; i <= 11 ; i++ )
53  {
54  if ( UTIL_ReadBackupRegister( i ) != 0 )
55  return TRUE;
56  }
57 
58  return FALSE;
59 }
60 
61 
62 /*******************************************************************************
63 *
64 * SetBitTimingAnalysis
65 *
66 *******************************************************************************/
76 /********************************************************************************/
77 void SetBitTimingAnalysis( u8 set )
78 {
79  if ( set )
80  {
81  CX_Write( CX_GPIO_PIN7, Bit_SET, 0 ); /* Systick interruption on CX_SPI_SCK */
82  }
83  else
84  {
85  CX_Write( CX_GPIO_PIN7, Bit_RESET, 0 ); /* Systick interruption on CX_SPI_SCK */
86  }
87 }
88 
90 
91 /*******************************************************************************
92 *
93 * UTIL_GetBat
94 *
95 *******************************************************************************/
103 /******************************************************************************/
104 u16 UTIL_GetBat( void )
105 {
106  u16 vbat;
107  vs32 i;
108 
109  // Measures VBAT and calculates the mean value
110  vbat = 0;
111  for ( i = 0; i < ADC_NB_SAMPLES; i++ )
112  {
113  vbat += ADC_ConvertedValue[0 + i * ADC_NB_CHANNELS];
114  }
115  vbat = vbat / ADC_NB_SAMPLES;
116 
117  vbat = vbat & 0xFFF;
118  vbat = ( vbat * VDD_VOLTAGE_MV ) / 0x1000;
119 
120  vbat *= 2; //Divider bridge Vbat <-> 1M -<--|-->- 1M <-> Gnd,
121 
122  if ( VBat == -1 )
123  {
124  VBat = vbat;
125  }
126  else
127  {
128  VBat = ( VBat >> 1 ) + ( vbat >> 1 );
129  }
130  return VBat;
131 }
132 
133 /*******************************************************************************
134 *
135 * UTIL_GetTemp
136 *
137 *******************************************************************************/
145 /******************************************************************************/
146 u16 UTIL_GetTemp( void )
147 {
148  u16 temp;
149  vs32 i;
150 
151  // Calculate the mean value
152  temp = 0;
153  for ( i = 0; i < ADC_NB_SAMPLES; i++ )
154  {
155  temp += ADC_ConvertedValue[1 + i*ADC_NB_CHANNELS];
156  }
157  temp = temp / ADC_NB_SAMPLES;
158 
159  temp = temp & 0xFFF;
160  temp = ( temp * VDD_VOLTAGE_MV ) / 0x1000; //finds mV
161  temp = ((( 1430 - temp ) * 100000 ) / 4300 ) + 25000; //gives approx temp x 1000 degrees C
162 
163  //Fahrenheit = 32 + 9 / 5 * Celsius
164  if ( fTemperatureInFahrenheit )
165  {
166  temp = 32000 + ( 9 * temp ) / 5 ;
167  }
168 
169  return temp / 100;
170 }
171 
172 
173 /*******************************************************************************
174 *
175 * UTIL_SetPll
176 *
177 *******************************************************************************/
188 /******************************************************************************/
189 void UTIL_SetPll( enum eSpeed speed )
190 {
191  /* Select internal clok as system clock source */
192  RCC_SYSCLKConfig( RCC_SYSCLKSource_HSI );
193 
194  /* Disable PLL */
195  RCC_PLLCmd( DISABLE );
196 #ifdef STM32F10X_CL
197  RCC_PLL2Cmd( DISABLE );
198 #endif
199 
200  if (( speed < SPEED_VERY_LOW ) || ( speed > SPEED_VERY_HIGH ) )
201  {
202  speed = SPEED_MEDIUM;
203  }
204 
205  CurrentSpeed = speed;
206 
207  switch ( speed )
208  {
209  // 18 MHz
210  case SPEED_VERY_LOW :
211 #ifdef STM32F10X_CL
212  // Source PLLCLK = PLL2
213  RCC->CFGR2 &= ( uint32_t )~( RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
214  RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC );
215  RCC->CFGR2 |= ( uint32_t )( RCC_CFGR2_PREDIV2_DIV4 | RCC_CFGR2_PLL2MUL12 |
216  RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_I2S2SRC );
217  /* PLL configuration: PLLCLK = (PLL2CLK / 16) * 6.5 = 17.97 MHz */
218  RCC->CFGR &= ( uint32_t )~( RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL );
219  RCC->CFGR |= ( uint32_t )( RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL6_5 );
220 #else
221  /* PLLCLK = 6MHz * 3 = 18 MHz */
222  RCC_PLLConfig( RCC_PLLSource_HSE_Div2, RCC_PLLMul_3 );
223 #endif
224  break;
225 
226  // 24MHz
227  case SPEED_LOW :
228 #ifdef STM32F10X_CL
229  // Source PLLCLK = PLL2
230  RCC->CFGR2 &= ( uint32_t )~( RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
231  RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC );
232  RCC->CFGR2 |= ( uint32_t )( RCC_CFGR2_PREDIV2_DIV4 | RCC_CFGR2_PLL2MUL12 |
233  RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_I2S2SRC );
234  /* PLL configuration: PLLCLK = (PLL2CLK / 9) * 5 = 24.58 MHz */
235  RCC->CFGR &= ( uint32_t )~( RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL );
236  RCC->CFGR |= ( uint32_t )( RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL5 );
237 #else
238  /* PLLCLK = 12MHz * 2 = 24 MHz */
239  RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_2 );
240 #endif
241  break;
242 
243  // 36MHz
244  default :
245  CurrentSpeed = SPEED_MEDIUM;
246  case SPEED_MEDIUM :
247 #ifdef STM32F10X_CL
248  // Source PLLCLK = PLL2
249  RCC->CFGR2 &= ( uint32_t )~( RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
250  RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC );
251  RCC->CFGR2 |= ( uint32_t )( RCC_CFGR2_PREDIV2_DIV4 | RCC_CFGR2_PLL2MUL12 |
252  RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_I2S2SRC );
253  /* PLL configuration: PLLCLK = (PLL2CLK / 8) * 6.5 = 35.94 MHz */
254  RCC->CFGR &= ( uint32_t )~( RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL );
255  RCC->CFGR |= ( uint32_t )( RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL6_5 );
256 #else
257  /* PLLCLK = 12MHz * 3 = 36 MHz */
258  RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_3 );
259 #endif
260  break;
261 
262  // 48MHz
263  case SPEED_HIGH :
264 #ifdef STM32F10X_CL
265  // Source PLLCLK = PLL2
266  RCC->CFGR2 &= ( uint32_t )~( RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
267  RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC );
268  RCC->CFGR2 |= ( uint32_t )( RCC_CFGR2_PREDIV2_DIV4 | RCC_CFGR2_PLL2MUL12 |
269  RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_I2S2SRC );
270  /* PLL configuration: PLLCLK = (PLL2CLK / 8) * 9 = 49.77 MHz */
271  RCC->CFGR &= ( uint32_t )~( RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL );
272  RCC->CFGR |= ( uint32_t )( RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9 );
273 #else
274  /* PLLCLK = 12MHz * 4 = 48 MHz */
275  RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_4 );
276 #endif
277  break;
278 
279  // 72MHz
280  case SPEED_VERY_HIGH :
281 #ifdef STM32F10X_CL
282  // Source PLLCLK = PLL2
283  RCC->CFGR2 &= ( uint32_t )~( RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
284  RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC );
285  RCC->CFGR2 |= ( uint32_t )( RCC_CFGR2_PREDIV2_DIV4 | RCC_CFGR2_PLL2MUL12 |
286  RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_I2S2SRC );
287  /* PLL configuration: PLLCLK = (PLL2CLK / 4) * 6.5 = 71.88 MHz */
288  RCC->CFGR &= ( uint32_t )~( RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL );
289  RCC->CFGR |= ( uint32_t )( RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL6_5 );
290 #else
291  /* PLLCLK = 12MHz * 6 = 72 MHz */
292  RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_6 );
293 #endif
294  break;
295  }
296 
297 #ifdef STM32F10X_CL
298  /* Enable PLL2 */
299  RCC_PLL2Cmd( ENABLE );
300 
301  /* Wait till PLL2 is ready */
302  while (( RCC->CR & RCC_CR_PLL2RDY ) == 0 )
303  {
304  }
305 #endif
306 
307  /* Enable PLL */
308  RCC_PLLCmd( ENABLE );
309 
310  /* Wait till PLL is ready */
311  while (( RCC->CR & RCC_CR_PLLRDY ) == 0 )
312  {
313  }
314 
315  /* Select PLL as system clock source */
316  RCC_SYSCLKConfig( RCC_SYSCLKSource_PLLCLK );
317 
318  /* Wait till PLL is used as system clock source */
319  while (( RCC->CFGR & ( uint32_t )RCC_CFGR_SWS ) != ( uint32_t )0x08 )
320  {
321  }
322 
323  /* This function fills a RCC_ClocksTypeDef structure with the current frequencies
324  of different on chip clocks (for debug purpose) */
325  RCC_GetClocksFreq( &RCC_ClockFreq );
326 
327 #if AUDIO_AVAIL
328 #ifndef STM32F10X_CL
329  extern const u16 I2S_PrescalerVal[];
330  // Set the prescaler values for the I2S (audio codec) according to the PLL
331  *( u16* )AUDIO_I2SPR = I2S_PrescalerVal[speed-1];
332 #endif
333 #endif
334 }
335 
336 
337 /*******************************************************************************
338 *
339 * UTIL_ReadBackupRegister
340 *
341 *******************************************************************************/
351 /******************************************************************************/
352 backup_t UTIL_ReadBackupRegister( index_t BKP_DR )
353 {
354  if ( BKP_DR < 11 )
355  {
356  return ( *( vu16* )( BKP_BASE + 4 * BKP_DR ) );
357  }
358  else if ( BKP_DR < 43 )
359  {
360  return ( *( vu16* )( BKP_BASE + 4 * ( BKP_DR + 5 ) ) );
361  }
362  else
363  return 0;
364 }
365 
366 /*******************************************************************************
367 *
368 * UTIL_WriteBackupRegister
369 *
370 *******************************************************************************/
379 /********************************************************************************/
380 void UTIL_WriteBackupRegister( index_t BKP_DR, backup_t Data )
381 {
382  if ( BKP_DR < 11 )
383  {
384  *( vu16* )( BKP_BASE + 4 * BKP_DR ) = Data;
385  }
386  else if ( BKP_DR < 43 )
387  {
388  *( vu16* )( BKP_BASE + 4 *( BKP_DR + 5 ) ) = Data;
389  }
390 }
391 
392 /*******************************************************************************
393 *
394 * UTIL_GetPrimerType
395 *
396 *******************************************************************************/
406 /********************************************************************************/
407 u16 UTIL_GetPrimerType( void )
408 {
409  return PRIMER_TYPE;
410 }
411 
412